1. Field of the Invention
The field of the invention relates to the field of data storage and in particular, to the storage and access of data in semiconductor memories.
2. Description of the Prior Art
There is a desire to reduce the size and power consumption of a memory. However, as the devices forming a memory and their power consumption reduce, their robustness to corruption tends to decrease. It is becoming increasingly challenging to design robust semiconductor memories such as SRAM that are both small and consume low power.
As dimensions scale down the variations in device property due to random dopant fluctuations, line edge roughness etc. increase drastically. Thus, designing a robust SRAM with these smaller dimensions where cells can be read (without read disturb) and written to across all operational voltage ranges turns out to be very difficult.
Several different designs for the bitcells forming an SRAM memory have been proposed to improve their robustness. A conventional SRAM memory cell is shown in FIG. 1. It has six transistors, two pass gate transistors NA and NB and four transistors that form a feedback loop for storing the data value. A bit line and complementary bit line feed data to and from the cell and the word line is used to provide the cell with access to the bit lines. In order to be able to write to the bit cell the input voltage must be high enough to switch the state of the cell if required, whilst when reading the state needs to remain uncorrupted.
Various different bit cells have been proposed that are more robust to read and or write operations. These tend to have additional transistors and thus, 7 transistor and 8 transistor bit cells are known that are more robust but take more area.
A five transistor bit cell is described in Nalam et al. “Asymmetric Sizing in a 45 nm 5T SRAM to Improve Read Stability over 6T” from Custom Integrated Circuits conference 2009 and is shown in FIG. 2. This 5T bit cell is asymmetrically sized to improve the read static noise margin. However, as data is only input from one side it is more difficult to switch the state when writing to the cell than is the case in the 6T cell. This is addressed by collapsing the VDDC powering the feedback loop and boosting the voltage on the word line to strengthen the access transistor during a write. The write noise margin is still inferior to the six transistor cell and requires a large voltage swing in both the voltage on the word line and on VDDC. Thus, although the five transistor cell could potentially provide area savings the irregular structure and need for write assist methods detract from these area benefits.
It would be desirable to increase the robustness of a memory to read and write margins without unduly increasing its area.